In the past two decades, sophisticated systems have evolved in the techniques to evaluate defects that affect the yield of integrated circuits. These systems include yield models generated in conjunction with the design of test vehicles (TV) that facilitate both yield prediction and yield enhancement of an integrated circuit manufacturing process. Except for the measurement of contact yields, (short flow) TV structures are utilized to evaluate defects on a single level.
In the case of full flow TV's, the prior art does not disclose how to identify the detailed interaction of defects in adjacent (vertical) levels through the results of electrical testing. For the case of the identification of defects on a single layer through optical and/or scanning electron microscope (SEM) inspection techniques it is difficult to predict what artifacts discovered on an inspected layer might produce killer defects in the next layer above it. That is, such inspection methods attempt to identify killer defects within the layer that is inspected.
U.S. Provisional Patent Application No. 60/316,317, filed Aug. 31, 2001, which is incorporated by reference herein in its entirety, addressed the design of TV's which characterize the interaction of feature induced defects within adjacent (vertical) layers related to the Copper damascene chemical mechanical polishing (CMP) processing geometries.
It is desirable that the next generation of yield models with yield predictive capabilities take into account the yield impact of the interaction of structural artifacts within multi-level process layers.